Memory cells of this type are used, for example, in dynamic random access memories (DRAMs). A DRAM chip contains a matrix of memory cells, which are arranged in the form of rows and columns and are addressed by word lines as control lines and bit lines as read-out lines. The read-out of data from the memory cells, or the writing of data to the memory cells, is realized by the activation of suitable word lines and bit lines.
Each of the memory cells contains a capacitor for the purpose of charge storage, the charge state in the capacitor representing a data bit. The memory cell usually further contains a transistor connected to a capacitor. The transistor has two diffusion regions separated from one another by a channel, which is controlled by a gate as a control terminal. Depending on the direction of the current flow, one diffusion region is designated as the drain and the other, as the source. The drain region is connected to the bit line, the source region is connected to the capacitor, and the gate is connected to the word line. By the application of suitable voltages to the gate, the transistor is controlled in such a way that a current flow between the drain region and the source region through the channel is switched on and off.
The charge stored in the capacitor decreases with time on account of leakage currents. Before the charge has decreased to an indeterminate level below a threshold value, the storage capacitor must be refreshed. For this reason, these memory cells are referred to as dynamic RAM (DRAM). Such a memory is discussed, for example, in the U.S. Pat. No. 5,867,420.
The central problem in the case of the known DRAM variants is that of producing a sufficiently large capacitance of the capacitor. This problem area will be aggravated in future by the advancing miniaturization of semiconductor components. The continuous increase in the integration density means that the area available per memory cell, and thus, the capacitance of the capacitor decrease ever further. An excessively small capacitance of the capacitor can adversely affect the functionality and usability of the memory device since an excessively small quantity of charge is stored on it.
By way of example, the sense amplifiers connected to the bit line require a sufficiently high signal level for a reliable read-out of the information held in the memory cell. The ratio of the storage capacitance to the bit line capacitance is crucial in determining the signal level. If the storage capacitance is too low, this ratio may be too small for the generation of an adequate signal.
A smaller storage capacitance likewise requires a higher refresh frequency since the quantity of charge stored in the capacitor is limited by its capacitance and additionally decreases due to leakage occurrence. If the quantity of charge in the storage capacitor falls below a minimum quantity of charge, then it is no longer possible to read out the information stored in it by the connected sense amplifiers; the information is lost and read errors occur.
According to a rule of thumb, the storage capacitance should be at least about 35 ff in order to obtain a sufficiently large read signal and sufficient insensitivity to alpha radiation. Using a dielectric, 10 nm thick, made of SiO2, with a dielectric constant (DC) of ∈r=4, requires a capacitor area of about 10 μm2. However, even with a 4M DRAM, there is already less area than 10 μm2 are available for the entire memory cell, thereby ruling out a purely planar arrangement of the capacitor.
It has therefore become necessary, in order to obtain sufficient storage capacitance for the capacitor layout, to utilize the third dimension, for example, by configuring the capacitor as a trench capacitor or stacked capacitor. With further miniaturization, the smaller area available can then be compensated for by means of an increase in the capacitance through the use of deeper trenches or higher stacks.
Another approach consists in using materials having a larger dielectric constant. By way of example, Si3N4 with a DC of 7 is used, in particular, in the form of ONO (oxide-nitride-oxide) and NO (nitride-oxide) sandwiches. In this case, a thermal oxide having a thickness of 2–3 nm is grown on the silicon, for example, in order to ensure a low interfacial state density. A silicon nitride layer having a thickness of 7–8 nm is then deposited and subsequently oxidized in order to obtain a second oxide layer having a thickness of 2–3 nm. This second oxide layer serves for preventing the tunneling of charge carriers by means of a high energy barrier.
Even the use of materials having an even higher DC, such as, for example, tantalum oxide (Ta2O5) or barium strontium titanate (BST), is possible although not unproblematic in terms of process engineering. With this possibility, the storage capacitance that can be achieved is upwardly limited by the dielectric constant and the thickness of the dielectric at which the latter still effects insulation.